 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Integrated Circuit Systems, Inc. ICS83947I LOW SKEW, 1-TO-9 LVCMOS FANOUT BUFFER FEATURES * 9 LVCMOS/LVTTL outputs * Selectable CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL * Maximum output frequency: 110MHz * Output skew: 500ps (maximum) * Part-to-part skew: 2ns (maximum) * 3.3V operating supply * -40C to 85C ambient operating temperature * Lead-Free package available * Pin compatible with the MPC947 GENERAL DESCRIPTION The ICS83947I is a low skew, 1-to-9 LVCMOS Fanout Buffer and a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from ICS. The low impedance LVCMOS/LVTTL outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 9 to 18 by utilizing the ability of the outputs to drive two series terminated lines. ICS Guaranteed output and part-to-part skew characteristics make the ICS83947I ideal for high performance, single ended applications that also require a limited output voltage. BLOCK DIAGRAM CLK_EN D Q LE CLK0 CLK1 0 PIN ASSIGNMENT GND GND GND VDDO VDDO Q0 Q1 Q2 32 31 30 29 28 27 26 25 Q0 GND CLK_SEL Q1 CLK0 CLK1 CLK_EN Q3 Q4 Q5 Q6 Q7 Q8 OE VDD GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 GND VDDO Q8 GND Q7 VDDO Q6 GND 24 23 22 GND Q3 VDDO Q4 GND Q5 VDDO GND 1 CLK_SEL Q2 ICS83947I 21 20 19 18 17 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View OE 83947AYI http://www.icst.com/products/hiperclocks.html 1 REV. B OCTOBER 11, 2004 Integrated Circuit Systems, Inc. ICS83947I LOW SKEW, 1-TO-9 LVCMOS FANOUT BUFFER Name GND Type Power Input Input Input Input Power Pullup Description Power supply ground. Clock select input. When HIGH, selects CLK1. When LOW, selects CLK0. LVCMOS / LVTTL interface levels. Pullup Reference clock inputs. LVCMOS / LVTTL interface levels. TABLE 1. PIN DESCRIPTIONS Number 1, 8, 9, 12, 16, 17, 20, 24, 25, 29, 32 2 3, 4 5 6 7 CLK_SEL CLK0, CLK1 CLK_EN OE VDD Pullup Clock enable. LVCMOS / LVTTL interface levels. Pullup Output enable. LVCMOS / LVTTL interface levels. Coree supply pin. 10, 14, 18, 22, 27, 31 VDDO Power Output supply pins. Q0 thru Q8 clock outputs. 11, 13, 15, 19, 21, Q8, Q7, Q6, Q5, Output 23, 26, 28, 30 Q4, Q3, Q2, Q1, Q0 LVCMOS / LVTTL interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol CIN C PD RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor Input Pulldown Resistor Output Impedance 5 Test Conditions Minimum Typical 4 25 51 51 7 12 Maximum Units pF pF K K TABLE 3. OUTPUT ENABLE Control Inputs OE 0 1 1 AND CLOCK ENABLE FUNCTION TABLE Output Q0:Q8 Hi-Z LOW Follows CLK input CLK_EN X 0 1 83947AYI http://www.icst.com/products/hiperclocks.html 2 REV. B OCTOBER 11, 2004 Integrated Circuit Systems, Inc. ICS83947I LOW SKEW, 1-TO-9 LVCMOS FANOUT BUFFER 4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V0.3V, TA = -40C TO 85C Symbol Parameter VDD VDDO IDD Coret Supply Voltage Output Supply Voltage Input Supply Current Test Conditions Minimum 3.0 3.0 Typical 3.3 3.3 33 Maximum 3.6 3.6 50 Units V V mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V0.3V, TA = -40C TO 85C Symbol Parameter VIH VIL IIN VOH VOL Input High Voltage Input Low Voltage Input Current CLK0, CLK1, CLK_SEL, OE, CLK_EN IOH = -20mA IOL = 20mA -100 2.5 0.4 Test Conditions Minimum 2 Typical Maximum 3.6 0.8 Units V V A V V Output High Voltage Output Low Voltage 83947AYI http://www.icst.com/products/hiperclocks.html 3 REV. B OCTOBER 11, 2004 Integrated Circuit Systems, Inc. ICS83947I LOW SKEW, 1-TO-9 LVCMOS FANOUT BUFFER Test Conditions CLK to Q Measured on rising edge @VDDO/2 Measured on rising edge @VDDO/2 tPeriod/2 - 800 CLK_EN to CLK CLK_EN to CLK 0 1 11 11 0.8V to 2.0V 0.2 1 Minimum 110 1.8 Typical Maximum 4.5 500 2 tPeriod/2 + 800 Units MHz ns ps ns ps ns ns ns ns ns ns TABLE 5. AC CHARACTERISTICS, VDD = VDDO = 3.3V0.3V, TA = -40C TO 85C Symbol Parameter fMAX Output Frequency tPD Propagation Delay, NOTE 1 Output Skew; NOTE 2, 5 Par t-to-Par t Skew; NOTE 3, 5 Output Pulse Width Clock Enable Setup Time; NOTE 6 Clock Enable Hold Time; NOTE 6 Output Enable Time; NOTE 4 Output Disable Time; NOTE 4 Output Rise Time tsk(o) tsk(pp) t PW tS tH tZL, tZH tLZ, tHZ tR Output Fall Time 0.8V to 2.0V 0.2 1 tF All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Setup and Hold times are relative to the rising edge of the input clock. 83947AYI http://www.icst.com/products/hiperclocks.html 4 REV. B OCTOBER 11, 2004 Integrated Circuit Systems, Inc. ICS83947I LOW SKEW, 1-TO-9 LVCMOS FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 1.65V 0.15V V DD SCOPE Qx V DDO 2 LVCMOS GND Qx V Qy DDO 2 tsk(o) -1.65V 0.15V 3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW PART 1 Qx V DDO 2 CLK0, CLK1 VDD 2 PART 2 Qy V DDO 2 tsk(pp) Q0:Q8 t PD VDDO 2 PART-TO-PART SKEW PROPAGATION DELAY V Q0:Q8 DDO 2 Pulse Width t PERIOD 2V 0.8V tR 2V 0.8V tF Clock Outputs odc = t PW t PERIOD OUTPUT RISE/FALL TIME 83947AYI OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD http://www.icst.com/products/hiperclocks.html 5 REV. B OCTOBER 11, 2004 Integrated Circuit Systems, Inc. ICS83947I LOW SKEW, 1-TO-9 LVCMOS FANOUT BUFFER RELIABILITY INFORMATION TABLE 6. JAVS. AIR FLOW TABLE FOR 32 LEAD LQFP JA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W 200 55.9C/W 42.1C/W 500 50.1C/W 39.4C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS83947I is: 1040 83947AYI http://www.icst.com/products/hiperclocks.html 6 REV. B OCTOBER 11, 2004 Integrated Circuit Systems, Inc. ICS83947I LOW SKEW, 1-TO-9 LVCMOS FANOUT BUFFER 32 LEAD LQFP PACKAGE OUTLINE - Y SUFFIX FOR TABLE 7. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM Reference Document: JEDEC Publication 95, MS-026 83947AYI http://www.icst.com/products/hiperclocks.html 7 REV. B OCTOBER 11, 2004 Integrated Circuit Systems, Inc. ICS83947I LOW SKEW, 1-TO-9 LVCMOS FANOUT BUFFER Marking ICS83947AYI ICS83947AYI ICS3947AYIN ICS3947AYIN Package 32 Lead LQFP 32 Lead LQFP on Tape and Reel 32 Lead "Lead-Free/Annealed" LQFP 32 Lead "Lead-Free/Annealed" LQFP on Tape and Reel Count 250 per tray 1000 250 per tray 1000 Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C TABLE 8. ORDERING INFORMATION Part/Order Number ICS83947AYI ICS83947AYIT ICS83947AYILN ICS83947AYILNT The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 83947AYI http://www.icst.com/products/hiperclocks.html 8 REV. B OCTOBER 11, 2004 Integrated Circuit Systems, Inc. ICS83947I LOW SKEW, 1-TO-9 LVCMOS FANOUT BUFFER REVISION HISTORY SHEET Description of Change AC Characterisitics Table, tS and tH rows- revised Test Conditions to read CLK_EN to CLK. Added Lead Free bullet in Features section. Pin Characteristics Table - changed CIN from 4pF max. to 4pF min. ROUT added 5 min and 12 max. Ordering Information Table - add Lead-Free par t. Updated format throughout data sheet. Date 6/21/02 Rev A Table T5 T2 Page 4 1 2 8 B T8 10/11/04 83947AYI http://www.icst.com/products/hiperclocks.html 9 REV. B OCTOBER 11, 2004 |
Price & Availability of ICS83947I
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |